This invention relates to the field of data transmission, and more particularly to a method and apparatus for decoding coded data having a regular pattern.
When it is desired to transmit data as a bit stream over a physical transmission medium, some means must be employed for converting the stream of 1xe2x80x2s and 0xe2x80x2s into physical signals. One technique for transmitting data over a physical link is known as xe2x80x9cManchester codingxe2x80x9d. In Manchester coded data, a xe2x80x9c1xe2x80x9d is coded as a short time period followed by a long time period, and a xe2x80x9c0xe2x80x9d is coded by a long time period followed by a short time period, where a long time period is twice a short time period.
In some applications, such as marking underground pipes, xe2x80x9ctagxe2x80x9d devices are employed. A tag is an electronic marker containing memory that can be read out by a remote reader. In a typical application the tag might be buried in the ground to mark where water, gas pipes and electrical wires are placed and by whom. The tag can be located and read by a reader that looks like a metal detector.
The tag contains a coil and a chip. There are no batteries since the tag uses the transmitted signal as a power source. Where data is transmitted to the chip using this kind of coding, it is not possible to have oscillators and counters on the chip because of the high current consumption at the frequencies required for time measurements. For ultra low power applications it is a continual challenge to design circuits with low current consumption in the decoding of data.
The present invention provides a decoder capable of ultra low power consumption that uses an analog decoding circuit. The invention takes advantage of the fact that in the case of a coding scheme consisting of a combination of short and long duration pulses having a predetermined interrelationship, such as a Manchester coding scheme, the average duty cycle of an output stream derived from one of said pulses is predictable.
According to the present invention there is provided a decoder for decoding a stream of encoded data bits, each data bit being represented by a coding scheme, comprising an input for receiving said stream of encoded data bits; an analog signal processor for generating output pulses from said stream of encoded data bits; and a feedback loop for providing a control signal to adjust a control parameter governing said analog signal processor so that the average duty cycle of said output pulses matches a predetermined expected relationship for said coding scheme.
The invention is based on the fact that the input signal has a predetermined coding scheme consisting of short and long duration pulses for each data bit. For example, in the case of Manchester coding each bit consists of a short and long period in each time slice defining a bit, so over a period of time the ratio of short or long periods to the total duration of a bit will be constant. The output data will have a regularity that can be measured and fedback as a control signal. When the output ratio, i.e. average duty cycle, matches the known ratio for the input signal, it follows that the device is accurately decoding the data.
The novel decoder can use analog decoding that also makes the circuit adaptive to different data rates and can be self trimmed, removing the need for trimming to compensate for process variations during manufacture.
The decoder also draws extremely low power compared to a digital implementation of a pulse distance decoder needed for any digitally coded data with a measurable regular pattern in it.
A simple RC-filter (charge pump) can be used to measure the voltage average of the output signal and feed back this to adjust the duty cycle of the output until the average value reaches the value that would be expected. The feedback signal changes the slope of the ramp in the circuit.
The invention further provides a method of a stream of encoded data bits, each data bit being represented by a coding scheme consisting of a combination of short and long duration pulses having a predetermined interrelationship, comprising receiving said stream of encoded data bits; generating output pulses from said stream of encoded data bits in an analog signal processor; and generating a feedback control signal from said output pulses to adjust said analog signal processor so that the average duty cycle of said output pulses matches a predetermined expected relationship for said coding scheme.